>> RISC-V isn't magically immune to spectre for no reason. Indeed. RISC-V is an ISA and says little about how any given implementation may accelerate branches

>> RISC-V isn't magically immune to spectre for no reason. Indeed. RISC-V is an ISA and says little about how any given implementation may accelerate branches or load cache lines. It's entirely feasible to create a CPU based on the RISC-V ISA that is vulnerable to these attacks. There are proprietary RISC-V implementations in the wild today that may or may not have such properties, and while these deeply embedded implementations are likely to be simple, in-order non-speculative processors we can't really know. Recently the RISC-V ISA was found to have an under specified memory model[1] that could manifest as memory ordering problems in more complex (and as yet hypothetical) implementations. This was discovered by Princeton researchers using a formal verification system. Since then RISC-V developers have been working[2] toward correcting this by fully specifying the RISC-V memory model (including two variants with different degrees of rigor.) To my mind this specific case argues that open design may see real benefits from public scrutiny. [1] https://www.electronicsweekly.com/open-source-engineering/risc-v-bugs-found-princeton-2017-04/ https://www.electronicsweekly.com/open-source-engineering/ri... [2] https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/hKywNHBkAXM https://groups.google.com/a/groups.riscv.org/forum/#!topic/i...