5 ms·
> In the good old days*, the speed of processors was well matched with the speed of memory access...Over the ensuing 35 years, processors have become very much
by Chaebixi 9y ago
> In the good old days*, the speed of processors was well matched with the speed of memory access...Over the ensuing 35 years, processors have become very much faster, but memory only modestly so: a single Cortex-A53 in a Raspberry Pi 3 can execute an instruction roughly every 0.5ns (nanoseconds), but can take up to 100ns to access main memory.
In real-world terms, what's the fastest processor we could build today whose execution speed is reasonably matched to it's main memory access speed (so it doesn't need caches, etc)?
I could imagine that a processor, with a simple design that closely matches a naive model of how CPUs work, would be very useful for high-security applications. It would be much easier to reason about up-front.
- gaius 9y agoIn the good old days, the speed of processors was well matched with the speed of memory access... In fact on the Beeb, spiritual ancestor of the RPi, memory ran at 4Mhz and the CPU at only 2Mhz...
- Chaebixi 9y agoIIRC, some of those old machines interleaved CPU and GPU memory access windows, since memory was so much faster than CPUs back then. Edit: this is what I'm talking about: https://www.bigmessowires.com/2011/08/25/68000-interleaved-memory-controller-design/ https://www.bigmessowires.com/2011/08/25/68000-interleaved-m...: > The Atari ST and Amiga appear to have both used a more aggressive scheme where video circuitry access occurred during known dead time in the 68000 bus cycle, so the CPU never had to wait
- jrowley 9y agoPeople use mainframes to this day for similar reasons.
- Chaebixi 9y agoThat doesn't make a ton of sense to me. Aren't mainframe CPUs developed using modern techniques?
- JdeBP 9y agoActually, mainframe CPUs are developed using old techniques, which are all of a sudden interesting again. (-: See for starters this discussion about reinventing the AS/400: https://news.ycombinator.com/item?id=16053518 https://news.ycombinator.com/item?id=16053518
- blattimwind 9y agoAt least some time ago IBM mainframes were powered by their regular POWER processors "just" with modified/extended microcode. Though it seems they also have dedicated CPUs for them, like the zEC12. (POWER doesn't really qualify as "old techniques")
- sitharus 9y agoModern DDR4 SDRAM can run up to 2133Mhz, but DDR SDRAM is designed to increase speed by taking advantage of CPU caches. For peak performance reads occur in batches so one read command also fill the cache with nearby data. SRAM can go fast since that’s what caches are made with, but that’s expensive. Also it would need to be close to the CPU as wire latency is non-trivial at high clock speeds.
- ZenoArrow 9y agoSomething I don't understand is why SRAM is more expensive than SDRAM. Is it just the manufacturing volumes and/or manufacturing yield, or are there architectural differences that make SRAM more expensive?
- cesarb 9y agoEach "bit" in SRAM is bigger than each "bit" in DRAM. Typical SRAM uses six transistors for each "bit", while typical DRAM uses one transistor and one capacitor. Bigger chips means less chips per wafer, and a larger chance for a chip to have a manufacturing defect.
- ZenoArrow 9y agoThank you for the explanation.
- Symmetry 9y agoThe problem isn't really the speed of the memory but its size. The planar nature of memory and the speed of light impose a latency of access on a pool of size N proportional to the square root of N. The L1 cache on your CPU has kept up in speed with the processor and is the same size as the memory computers had when computers could access their main memory quickly.
- blattimwind 9y agoThe latency of DRAM is mostly governed by Dennard scaling ("regardless of transistor size, power density remains the same"), because it means that making cells smaller reduces the available charge currents for bit-lines and the like proportionally, so only a small latency advantage can be gained.