3 ms·
https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/Intel-Analysis-of-Speculative-Execution-Side-Channels.pdf https://newsroom.intel.com/wp-content/u
by gcbirzan 9y ago
https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/Intel-Analysis-of-Speculative-Execution-Side-Channels.pdf https://newsroom.intel.com/wp-content/uploads/sites/11/2018/... - processors older than 5 years don't need a microcode update, and probably won't even benefit. The new instructions for preventing variant 2 is inferior to retpolines, even according to Intel...
- kbwt 9y ago> Note that the insertion of LFENCE must be done judiciously; if it is used too liberally, performance may be significantly compromised. Wow, as if we could press some magic button and it would pinpoint all the places where a branch condition involves user-controlled data. Of course Intel is downplaying this one to the max, the performance implications for a thorough fix are devastating.
- gcbirzan 9y agoIt's okay, retpolines are similarly so for C++: https://reviews.llvm.org/D41723 https://reviews.llvm.org/D41723 Again, obviously, not all indirect jumps need this, but still, Intel's fix might be even worse.
- kbwt 9y agoIt's not the indirect jumps that concern me but all the conditional branches, such as loop conditions.