6 ms·

This image is linked in the e-mail thread, with (some of?) the errata: https://www.geek.com/images/geeknews/2006Jan/core_duo_errata__2006_01_21__full.gif https:

This image is linked in the e-mail thread, with (some of?) the errata: https://www.geek.com/images/geeknews/2006Jan/core_duo_errata__2006_01_21__full.gif https://www.geek.com/images/geeknews/2006Jan/core_duo_errata... I'm just surprised that the URL is still valid after 12 years!

userbinator 9y ago
Is it just me or do AE4 and AE11 have the same description (REP MOVS crossing pages of different types) yet completely different classification/impact? IIRC this behaviour is now documented in the official manuals as "by design" since it was like that since the P3.
deleted 9y ago
[deleted]
agumonkey 9y ago
same, and don't bother reading too much, the best bugs came after ... incredible how I (we) ran on buggy hardware for so long. We should fund a tiny group for sane cpu design.
- alex_duf 9y ago
  That would be great. I know nothing about low level programming, and I'm wondering if webassembly couldn't be a good place to start designing CPU instruction sets? Can someone more competent on the matter tell me if this idea is crazy?
  - protomikron 9y ago
    > Can someone more competent on the matter tell me if this idea is crazy? Yes, it's crazy. :) But seriously, the ISA (instruction set architecture) is not the problem, but the optimizations (deep pipelines and speculative execution, etc.) are.
    - alex_duf 9y ago
      thanks!
    - dboreham 9y ago
      The nature of the ISA can influence the kinds of optimizations undertaken.
- busterarm 9y ago
  > We should fund a tiny group for sane cpu design. It's happened, again and again. The ARM CPUs powering your phones are a good example. Maybe with more of a market, POWER9 prices might come down.
  - agumonkey 9y ago
    Half recent application class arm core are affected. They are saner but the problem is still here
    - busterarm 9y ago
      I was more trying to point to RISC in general ("RISC is good" https://www.youtube.com/watch?v=wPrUmViN_5c https://www.youtube.com/watch?v=wPrUmViN_5c). What I really wanted to say is that we've tried but RISC hasn't really been successful in the (mass consumer) market, which because of ARM is only partially true. In truth you're correct, and ARM is sort of an unruly mess at this point, but that's a much larger discussion.
- equalunique 9y ago
  Order your Raptor Engineering Talos™ II now! Improved with PCI Express 4.0, CAPI 2.0, DDR4 RAM, & POWER9 CPU. https://raptorcs.com/TALOSII/ https://raptorcs.com/TALOSII/
  - agumonkey 9y ago
    but power is not immune from this right ?
    - equalunique 9y ago
      According to Raptor Engineering on Jan 5: "#POWER8 and prerelease variants of #POWER9 vulnerable to #Meltdown (CVE-2017-5754) and #Spectre (CVE-2017-5753 / CVE-2017-5715). #POWER9 is being patched and will not be vulnerable at ship, and there will be no performance loss versus current #POWER9 samples. Patches coming soon."[0] [0] https://twitter.com/RaptorCompSys/status/949368929507520517 https://twitter.com/RaptorCompSys/status/949368929507520517
- vanderZwan 9y ago
  The Mill computing people seem to have figured out quite a lot of elegant yet fast security solutions[0][1]. One simple example is the zero-bit. I don't have time to look up the exact details now, but IIRC, it's a simple hardware bit-flag that is part of the metadata of any value that can be read. If set, reading out that value returns zero. If not, it returns the actual value. Data defaults to having the zero-bit set, and the only way to unset a zero bit is writing new data into whatever you want to read from. The exact mechanism is probably a bit different, but that's how I remember it. Regardless of what the precise implementation is, the point is that by adding some smart hardware-based metadata like this in the form of bit-wise flags, you don't have to worry about having to manually wipe the data in memory once you are done with it (and have the speed benefits of not having to do so as well), yet still get all the safety benefits of never having to worry about buffer overflows and whatnot again. [0] https://millcomputing.com/ https://millcomputing.com/ [1] https://millcomputing.com/docs/security/ https://millcomputing.com/docs/security/

userbinator 9y ago

Is it just me or do AE4 and AE11 have the same description (REP MOVS crossing pages of different types) yet completely different classification/impact? IIRC this behaviour is now documented in the official manuals as "by design" since it was like that since the P3.

deleted 9y ago

[deleted]

agumonkey 9y ago

same, and don't bother reading too much, the best bugs came after ... incredible how I (we) ran on buggy hardware for so long. We should fund a tiny group for sane cpu design.

alex_duf 9y ago
That would be great. I know nothing about low level programming, and I'm wondering if webassembly couldn't be a good place to start designing CPU instruction sets? Can someone more competent on the matter tell me if this idea is crazy?
- protomikron 9y ago
  > Can someone more competent on the matter tell me if this idea is crazy? Yes, it's crazy. :) But seriously, the ISA (instruction set architecture) is not the problem, but the optimizations (deep pipelines and speculative execution, etc.) are.
  - alex_duf 9y ago
    thanks!
  - dboreham 9y ago
    The nature of the ISA can influence the kinds of optimizations undertaken.
busterarm 9y ago
> We should fund a tiny group for sane cpu design. It's happened, again and again. The ARM CPUs powering your phones are a good example. Maybe with more of a market, POWER9 prices might come down.
- agumonkey 9y ago
  Half recent application class arm core are affected. They are saner but the problem is still here
  - busterarm 9y ago
    I was more trying to point to RISC in general ("RISC is good" https://www.youtube.com/watch?v=wPrUmViN_5c https://www.youtube.com/watch?v=wPrUmViN_5c). What I really wanted to say is that we've tried but RISC hasn't really been successful in the (mass consumer) market, which because of ARM is only partially true. In truth you're correct, and ARM is sort of an unruly mess at this point, but that's a much larger discussion.
equalunique 9y ago
Order your Raptor Engineering Talos™ II now! Improved with PCI Express 4.0, CAPI 2.0, DDR4 RAM, & POWER9 CPU. https://raptorcs.com/TALOSII/ https://raptorcs.com/TALOSII/
- agumonkey 9y ago
  but power is not immune from this right ?
  - equalunique 9y ago
    According to Raptor Engineering on Jan 5: "#POWER8 and prerelease variants of #POWER9 vulnerable to #Meltdown (CVE-2017-5754) and #Spectre (CVE-2017-5753 / CVE-2017-5715). #POWER9 is being patched and will not be vulnerable at ship, and there will be no performance loss versus current #POWER9 samples. Patches coming soon."[0] [0] https://twitter.com/RaptorCompSys/status/949368929507520517 https://twitter.com/RaptorCompSys/status/949368929507520517
vanderZwan 9y ago
The Mill computing people seem to have figured out quite a lot of elegant yet fast security solutions[0][1]. One simple example is the zero-bit. I don't have time to look up the exact details now, but IIRC, it's a simple hardware bit-flag that is part of the metadata of any value that can be read. If set, reading out that value returns zero. If not, it returns the actual value. Data defaults to having the zero-bit set, and the only way to unset a zero bit is writing new data into whatever you want to read from. The exact mechanism is probably a bit different, but that's how I remember it. Regardless of what the precise implementation is, the point is that by adding some smart hardware-based metadata like this in the form of bit-wise flags, you don't have to worry about having to manually wipe the data in memory once you are done with it (and have the speed benefits of not having to do so as well), yet still get all the safety benefits of never having to worry about buffer overflows and whatnot again. [0] https://millcomputing.com/ https://millcomputing.com/ [1] https://millcomputing.com/docs/security/ https://millcomputing.com/docs/security/