3 ms·
> what have these flush and prefetch instructions ever done for us? Flushing the cache is important when the data must be in the main memory, for instance when
by cesarb 9y ago
> what have these flush and prefetch instructions ever done for us?
Flushing the cache is important when the data must be in the main memory, for instance when an I/O device does DMA to it and is not coherent with the caches. As for prefetch instructions, they are hard to use correctly, but in some cases can make an algorithm much faster.
- iforgotpassword 9y agoGood point, so could we make it "just write back but don't evict", something like fsync() for memory...?
- cesarb 9y agoThat works only for the CPU->device direction. For the device->CPU direction, you have to evict so the next load will get the data the device wrote.
- AnimalMuppet 9y agoIt occurs to me that a better solution, rather than having the CPU know when something else is going to write to the memory, is to have the memory tell the CPU when something else wrote to it. That would take a whole new memory protocol, though, and a new generation of CPU chips to use it...
- david-gpu 9y agoIf you are interested about this sort of thing, I suggest reading "Computer Architecture: A quantitative approach" by Hennessy and Patterson.
- ethbro 9y agoWe used "Computer Organization and Design: the Hardware/Software Interface" (also Hennessy and Patterson) as our comp arch textbook. I'd recommend it (any moderately recent version) for simply learning as well. Learning the internals of everything between memory and functional CPU subunits is fun (and useful). And the ideas don't change that quickly (e.g. the TLB and ROBs that were attacked here have been around for decades in similar form). There's only so many clever things you can do when a one bit buffer is expensive.
- esaym 9y agoWhich edition? I think we used the 3rd edition in our class 5 or so years ago. It would not be something I'd "recommend" but I haven't looked elsewhere ( just assuming there is something better out there)
- ethbro 9y agoI couldn't say. I do remember at the time searching for a few topics on the net -- and sadly it was one of those "black holes" where there simply isn't equivalent information out there. I imagine there might be some stuff in research papers, but that seems like an even worse learning experience. For example: https://www.google.com/search?q=branch+prediction+scoreboarding https://www.google.com/search?q=branch+prediction+scoreboard...
- deleted 9y ago[deleted]
- Unklejoe 9y agoAren't most modern CPU's cache coherent? I know the recent PowerPC SoC I was working with was. All of the DMA cache sync functions were no-ops in the Linux kernel for that architecture.
- noselasd 9y agoFor many architectures the coherency is turned off and managed in software by the device driver, to achieve better performance.
- Unklejoe 9y agoAny examples of this in the Linux kernel? Not doubting you, I'm just curious. I would think this would be device driver specific rather than architecture specific. Most drivers I've seen just use the kernel's DMA API (dma_alloc_coherent), which is guaranteed to provide a buffer that doesn't require any explicit cache management. If the architecture is coherent, then it leaves caching turned on for those pages. If it's non-coherent, then it turns it off.
- david-gpu 9y agoOn mobile SoCs the GPU is commonly not cache coherent with the CPU. Same with many of the other cores in the SoC.
- dingo_bat 9y agoI don't think that is needed on x86, since cache coherence is guaranteed in a very strong way. Maybe needed on ARM, but hey, if you're running ARM we already know you don't care about performance ;) All in all I think the only legit use may be in benchmarks.