4 ms·

These exploits are the result of the games we play to get high performance when memory is slow but processors are fast (speculative execution; caches). It's ti

These exploits are the result of the games we play to get high performance when memory is slow but processors are fast (speculative execution; caches). It's time to figure out how to make RAM dense, cheap, AND fast, so we can finally eliminate the cache layer from the ridiculous hierarchy of storage technologies.

mort96 9y ago
It will take a LONG time before we have tens of gigabytes of memory running with the same bandwidth and latency as L1 cache. According to a StackOverflow question [1], an L1 cache hit takes just over 2 nanoseconds, while RAM takes upwards of 100 nanoseconds. [1] https://stackoverflow.com/questions/4087280/approximate-cost-to-access-various-caches-and-main-memory https://stackoverflow.com/questions/4087280/approximate-cost...
elihu 9y ago
I don't think that's realistic; registers and SRAM are a lot more expensive than DRAM and consume a lot more power. I think having some combination of fast, expensive RAM and slow, cheap RAM in any system larger than a tiny microcontroller is just a fact of life. A different way to attack this problem is to make timing attacks harder by disallowing programs from reading the current time or inferring the passage of time by monitoring non-deterministic interactions between threads. Pure Haskell code (i.e. code that runs outside the IO monad) is an example of an execution environment that conceals timing from the running code. There are certain kinds of problems that aren't amenable to running in a completely side-effect and non-determinism free sandbox, but maybe for some applications it's a viable solution.
ahh 9y ago
Flops are cheap. Bandwidth is expensive. Latency is physics. We aren't at full lightspeed latencies ram technologies, but we're closer than you may realize, and it's unlikely we can do substantially better any time soon without revolutionary advances.
- dreamcompiler 9y ago
  Curious. So you're suggesting that if we substituted SRAM for DRAM (assuming it was just as cheap and dense), that the absence of CAS latency, refresh, and capacitors wouldn't make much difference because offchip speed-of-light delays dominate? [Edit] I realize it would always be slower than on-chip cache, but I thought it would still be at least an OOM faster then conventional DDRx DRAM.
- user5994461 9y ago
  Electricity moves around 2/3 of light speed.
  - leni536 9y ago
    More precisely the electromagnetic waves on the waveguides of the motherboard (bus) move around 2/3 as fast as electromagnetic waves in vacuum. Not as fundamentally separated as one would imagine.

mort96 9y ago

It will take a LONG time before we have tens of gigabytes of memory running with the same bandwidth and latency as L1 cache. According to a StackOverflow question [1], an L1 cache hit takes just over 2 nanoseconds, while RAM takes upwards of 100 nanoseconds. [1] https://stackoverflow.com/questions/4087280/approximate-cost-to-access-various-caches-and-main-memory https://stackoverflow.com/questions/4087280/approximate-cost...

elihu 9y ago

I don't think that's realistic; registers and SRAM are a lot more expensive than DRAM and consume a lot more power. I think having some combination of fast, expensive RAM and slow, cheap RAM in any system larger than a tiny microcontroller is just a fact of life. A different way to attack this problem is to make timing attacks harder by disallowing programs from reading the current time or inferring the passage of time by monitoring non-deterministic interactions between threads. Pure Haskell code (i.e. code that runs outside the IO monad) is an example of an execution environment that conceals timing from the running code. There are certain kinds of problems that aren't amenable to running in a completely side-effect and non-determinism free sandbox, but maybe for some applications it's a viable solution.

ahh 9y ago

Flops are cheap. Bandwidth is expensive. Latency is physics. We aren't at full lightspeed latencies ram technologies, but we're closer than you may realize, and it's unlikely we can do substantially better any time soon without revolutionary advances.

dreamcompiler 9y ago
Curious. So you're suggesting that if we substituted SRAM for DRAM (assuming it was just as cheap and dense), that the absence of CAS latency, refresh, and capacitors wouldn't make much difference because offchip speed-of-light delays dominate? [Edit] I realize it would always be slower than on-chip cache, but I thought it would still be at least an OOM faster then conventional DDRx DRAM.
user5994461 9y ago
Electricity moves around 2/3 of light speed.
- leni536 9y ago
  More precisely the electromagnetic waves on the waveguides of the motherboard (bus) move around 2/3 as fast as electromagnetic waves in vacuum. Not as fundamentally separated as one would imagine.