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RISC-V is an ISA, so it depends on the implementation.
by Keyframe 9y ago
RISC-V is an ISA, so it depends on the implementation.
- phkahler 9y agoFrom one of the papers: >> While makeshift processor-specific countermeasures are possible in some cases, sound solutions will require fixes to processor designs as well as updates to instruc- tion set architectures (ISAs) to give hardware architects and software developers a common understanding as to what computation state CPU implementations are (and are not) permitted to leak.