5 ms·
Not that we currently know about. RISC instead of CISC is better here as it shortens the pipeline, but even RISC processors do speculative predictions due to th
by richardwhiuk 9y ago
Not that we currently know about. RISC instead of CISC is better here as it shortens the pipeline, but even RISC processors do speculative predictions due to the cost of waiting till a branch is fully decided.
- alkonaut 9y agoWhat about more radically different designs? E.g Mill or others?
- mike_hearn 9y agoThe Mill does prediction: https://millcomputing.com/docs/prediction/ https://millcomputing.com/docs/prediction/ It has to. The problem is the speed of light here, not a simple slipup by a CPU designer.
- alkonaut 9y agoSo all that needs to be done is make 64GB L1 on the die...
- richardwhiuk 9y agoNot possible - the physical size of 64GB (even at nm scale) means that the time it takes for a signal to traverse it causes memory to take a long time to access, meaning you need a L0 cache to maintain performance.
- ant6n 9y agoWe need to go 3d
- deleted 9y ago[deleted]
- gpderetta 9y agoThe vulnerability window is proportional to the size of the reorder buffer (hundreds of instructions); the pipeline length (tens of stages) is not important (except on strictly in order CPUs with no reorder buffer I guess). Also modern OoO CISCs and RISCs have very similar pipeline depths for the same performance/power budget.