4 ms·
The whitepaper linked from this article introduces a new memory barrier named "CSDB". Does this work with existing ARM CPUs, and if so, how? I guess they could
by MarkSweep 9y ago
The whitepaper linked from this article introduces a new memory barrier named "CSDB". Does this work with existing ARM CPUs, and if so, how? I guess they could have always had this instruction encoding defined but just never gave it a name, but the seems a little odd.
- palotasb 9y agoAccording to the table here [1] it is a DSB (data synch barrier) instruction. I don't know if it corresponds to any of the listed valid option values in [2]. [1] http://kitoslab-eng.blogspot.nl/2012/10/armv8-aarch64-instruction-encoding.html http://kitoslab-eng.blogspot.nl/2012/10/armv8-aarch64-instru... [2] http://infocenter.arm.com/help/topic/com.arm.doc.dui0802b/CIHGHHIE.html http://infocenter.arm.com/help/topic/com.arm.doc.dui0802b/CI...