I think this could occur on any CPU that doesn't have a separate TLB for kernel mode and has speculative execution. So far it looks like it only occurs on Intel

I think this could occur on any CPU that doesn't have a separate TLB for kernel mode and has speculative execution. So far it looks like it only occurs on Intel's CPUs but I don't think that has anything to do with RISC vs CISC. I believe Linux was at least looking at applying this change to arm64 as well and this is likely going to lead to a design change in RISC-V to avoid having issues like this so it can happen to RISC designs as well.