3 ms·
So is this sort of issue more likely to occur on a non-RISC chip because of added complexity? I know extremely little about microprocessor design beyond the 101
by johnjones4 9y ago
So is this sort of issue more likely to occur on a non-RISC chip because of added complexity? I know extremely little about microprocessor design beyond the 101 knowledge from college so forgive my ignorance.
- amaranth 9y agoI think this could occur on any CPU that doesn't have a separate TLB for kernel mode and has speculative execution. So far it looks like it only occurs on Intel's CPUs but I don't think that has anything to do with RISC vs CISC. I believe Linux was at least looking at applying this change to arm64 as well and this is likely going to lead to a design change in RISC-V to avoid having issues like this so it can happen to RISC designs as well.