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How does this compare to the various other languages that compile to Verilog? Update: read the paper and they cover a few examples in it. Don't have enough dom

How does this compare to the various other languages that compile to Verilog? Update: read the paper and they cover a few examples in it. Don't have enough domain knowledge to judge whether the claims are accurate, nor whether they generalise to something like clash-lang.

kev009 9y ago
Chisel has better type safety than Verilog yet it's much less verbose than VHDL. Verilog is the industrial language of choice at most ASIC shops, and there are things like VerilogAMS (mixed signal) and SystemVerilog (validation) that will keep it entrenched for a long time. If you didn't have to care about ecosystem, my amateur opinion is that Chisel > VHDL > SystemVerilog > Verilog. I wasn't sure how seriously to take Chisel until I saw the RISC-V BOOM definition https://github.com/ucb-bar/riscv-boom https://github.com/ucb-bar/riscv-boom. It's clean, succinct, and I think Chisel is quite viable. It's also a testament to the symbolic nature of Scala. It holds together pretty well in JVM, ScalaJS, Chisel, and scala-native. Scala as a language is remarkably simple at the core, which Odersky does a good job of showing in his book, even though there are a lot of library features on top that make it complex and a more difficult language in general use. In this way of having a cute core, it is very unlike C++.
- dnautics 9y ago
  The verilog it generates, however, is on the edge of readable, which makes it a problem if you need to debug something using waveforms. I tried to make a verilog DSL in julia, which was a lot of fun, but I got stuck on how to implement sequential logic (instead of just combinatorial logic). Even better (and should be reasonably doable with clever application of julia's macro and type system) would be to take a julia function and transparently generate verilog from it.
  - _chris_ 9y ago
    I myself have had little difficulty in debugging Chisel designs using waveforms: virtually every Chisel node has its name maintained in Verilog. Sure, there are many, many more temporary variables created between nodes, but what I care about when debugging is "what are the values of my Chisel nodes"? It's like debugging by looking at assembly, but with your C/C++ variable names carried through to the disassembly.
  - Dolu 9y ago
    Checkout SpinalHDL it keep much more of your hardware description semantic inside the generated Verilog

kev009 9y ago

Chisel has better type safety than Verilog yet it's much less verbose than VHDL. Verilog is the industrial language of choice at most ASIC shops, and there are things like VerilogAMS (mixed signal) and SystemVerilog (validation) that will keep it entrenched for a long time. If you didn't have to care about ecosystem, my amateur opinion is that Chisel > VHDL > SystemVerilog > Verilog. I wasn't sure how seriously to take Chisel until I saw the RISC-V BOOM definition https://github.com/ucb-bar/riscv-boom https://github.com/ucb-bar/riscv-boom. It's clean, succinct, and I think Chisel is quite viable. It's also a testament to the symbolic nature of Scala. It holds together pretty well in JVM, ScalaJS, Chisel, and scala-native. Scala as a language is remarkably simple at the core, which Odersky does a good job of showing in his book, even though there are a lot of library features on top that make it complex and a more difficult language in general use. In this way of having a cute core, it is very unlike C++.

dnautics 9y ago
The verilog it generates, however, is on the edge of readable, which makes it a problem if you need to debug something using waveforms. I tried to make a verilog DSL in julia, which was a lot of fun, but I got stuck on how to implement sequential logic (instead of just combinatorial logic). Even better (and should be reasonably doable with clever application of julia's macro and type system) would be to take a julia function and transparently generate verilog from it.
- _chris_ 9y ago
  I myself have had little difficulty in debugging Chisel designs using waveforms: virtually every Chisel node has its name maintained in Verilog. Sure, there are many, many more temporary variables created between nodes, but what I care about when debugging is "what are the values of my Chisel nodes"? It's like debugging by looking at assembly, but with your C/C++ variable names carried through to the disassembly.
- Dolu 9y ago
  Checkout SpinalHDL it keep much more of your hardware description semantic inside the generated Verilog