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The text as written only seeks to defend AMD's product. Whether the sub text goes further is open to non objective speculation. Having said that I'm sure AMD ar

The text as written only seeks to defend AMD's product. Whether the sub text goes further is open to non objective speculation. Having said that I'm sure AMD are feeling pretty happy with their statement. Schadenfreude may be too long a bow...

rurban 9y ago
What are you talking about? Every other single CPU vendor with an MMD, arm, s390, Sparc, ... either has a separate page translation table register for kernel and user space, or like AMD memory page capabilities, just Intel not. It's very clear who is at fault here.
- amluto 9y ago
  Not ARM. You're confusing kernel mode with kernel addresses.
  - rurban 9y ago
    Nope, read the paper, read the patches. Only Intel is affected. Arm has two such registers, TTB0 and TTB1. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0333h/I1029222.html http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....
    - amluto 9y ago
      I think you're still misunderstanding. The CPU picks TTBR0 or TTBR1 based on the top significant bit of the VA, irrespective of whether the access was initiated by user or kernel code. This is in contrast to s390, which has separate page tables for user mode and kernel mode. I personally much prefer s390's model. And yes, I've read quite a few papers, and I wrote a good fraction of the patches.
      - rurban 9y ago
        Oh, thanks. My fault then. I haven't read the arm patches, only the summary.
      - kev009 9y ago
        I vaguely remember some threads from last decade where Linus trashed PowerPC and s390 TLBs. I wish I could find them and reread with this in mind.
        stefanfisk 9y ago
        are you thinking of this? http://yarchive.net/comp/powerpc_page_tables.html http://yarchive.net/comp/powerpc_page_tables.html
- tankenmate 9y ago
  My response was about whether AMD was part taking in schadenfreude, in reference to the OP's statement that this was "a big FU to Intel". I wasn't making a statement on who else was affected and/or who was at fault.

rurban 9y ago

What are you talking about? Every other single CPU vendor with an MMD, arm, s390, Sparc, ... either has a separate page translation table register for kernel and user space, or like AMD memory page capabilities, just Intel not. It's very clear who is at fault here.

amluto 9y ago
Not ARM. You're confusing kernel mode with kernel addresses.
- rurban 9y ago
  Nope, read the paper, read the patches. Only Intel is affected. Arm has two such registers, TTB0 and TTB1. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0333h/I1029222.html http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....
  - amluto 9y ago
    I think you're still misunderstanding. The CPU picks TTBR0 or TTBR1 based on the top significant bit of the VA, irrespective of whether the access was initiated by user or kernel code. This is in contrast to s390, which has separate page tables for user mode and kernel mode. I personally much prefer s390's model. And yes, I've read quite a few papers, and I wrote a good fraction of the patches.
    - rurban 9y ago
      Oh, thanks. My fault then. I haven't read the arm patches, only the summary.
    - kev009 9y ago
      I vaguely remember some threads from last decade where Linus trashed PowerPC and s390 TLBs. I wish I could find them and reread with this in mind.
      - stefanfisk 9y ago
        are you thinking of this? http://yarchive.net/comp/powerpc_page_tables.html http://yarchive.net/comp/powerpc_page_tables.html
tankenmate 9y ago
My response was about whether AMD was part taking in schadenfreude, in reference to the OP's statement that this was "a big FU to Intel". I wasn't making a statement on who else was affected and/or who was at fault.