3 ms·
One possible vector suggested by Matt Tait (pwnallthethings) on Twitter: if speculative operations can influence what the processor does with the cache, the re
by rst 9y ago
One possible vector suggested by Matt Tait (pwnallthethings) on Twitter: if speculative operations can influence what the processor does with the cache, the results can be observed with cache timing attacks. If the branch predictor reads the results of speculative operations, it's real easy, as he suggests here:
https://twitter.com/pwnallthethings/status/947978927284383744 https://twitter.com/pwnallthethings/status/94797892728438374...
but (as he notes elsewhere) there are plenty of other channels in an Intel processor for information to leak...
- Taniwha 9y agomy guess is that the cache tags or tlb entries loaded on failed speculative accesses are wrong (maybe the valid bit is set but the address wasn't changed, or the user/supervisor protections are munged), that could leave you with a cache line or page tagged as user accessible but really protected kernel data