4 ms·

maybe just support? a long time ago, when microcoded architectures were the default, i did some work at that level. without having access to the processor desi

maybe just support? a long time ago, when microcoded architectures were the default, i did some work at that level. without having access to the processor design itself it was pretty rough going. lots of back and forth, trial and error, cycle counting. there really isn't any intermediate abstraction layer you can define. and how much are you really going to enable? some funny bit ops? some explicitly interleaved fetch and computation? its pretty cool to try to understand things, but is it worth it for Intel? alot of stuff seems to baked in hardware too...pretty sure the cache coherency protocol isn't on the table...maybe some different concurrency primitives?

bogomipz 9y ago
>" a long time ago, when microcoded architectures were the default,..." They are default the now though. As far as I know hardwired control logic wasn't used for very long before people moved to using microcode. Maybe I am misunderstanding that part of your comment?
- userbinator 9y ago
  It's a combination of microcode and hardwired logic that's common now --- hardwired simple instructions, microcoded complex ones.
  - bogomipz 9y ago
    In the slide during the presentation at the 10:23 minute mark he shows the short decoders under the instruction register and I believe even those simple instructions are all made up of micro-ops that need to be looked up in ROM as well.
    - monocasa 9y ago
      The CPU only executes micro ops, but the "vector decoder" is the only one that uses microcode to sequence the ops.
      - deleted 9y ago
        [deleted]
- pfalcon 9y ago
  You must be kidding. Normal CPU architectures - the RISC ones - don't have funny things like "microcode" (well, true RISCs don't have it for sure). Majority of CPU architectures nowadays are RISCs. Some legacy ones, like x86, are CISC-translated-to-RISC, as this presentation shows. The native RISC code in them is called "microcode".
  - bogomipz 9y ago
    Oh yes I was just kidding. Can we assume you must be kidding too when you use the phrase "Normal CPU architectures"?

bogomipz 9y ago

>" a long time ago, when microcoded architectures were the default,..." They are default the now though. As far as I know hardwired control logic wasn't used for very long before people moved to using microcode. Maybe I am misunderstanding that part of your comment?

userbinator 9y ago
It's a combination of microcode and hardwired logic that's common now --- hardwired simple instructions, microcoded complex ones.
- bogomipz 9y ago
  In the slide during the presentation at the 10:23 minute mark he shows the short decoders under the instruction register and I believe even those simple instructions are all made up of micro-ops that need to be looked up in ROM as well.
  - monocasa 9y ago
    The CPU only executes micro ops, but the "vector decoder" is the only one that uses microcode to sequence the ops.
    - deleted 9y ago
      [deleted]
pfalcon 9y ago
You must be kidding. Normal CPU architectures - the RISC ones - don't have funny things like "microcode" (well, true RISCs don't have it for sure). Majority of CPU architectures nowadays are RISCs. Some legacy ones, like x86, are CISC-translated-to-RISC, as this presentation shows. The native RISC code in them is called "microcode".
- bogomipz 9y ago
  Oh yes I was just kidding. Can we assume you must be kidding too when you use the phrase "Normal CPU architectures"?