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Question for folks here who've worked on these 1 Billion+ transistor chips. How relevant is stuff like K-Maps in your day-to-day work? Is this stuff done by too

Question for folks here who've worked on these 1 Billion+ transistor chips. How relevant is stuff like K-Maps in your day-to-day work? Is this stuff done by tools like Mentor-Graphics and Synopsis or do folks still lay this out by hand?

gchadwick 9y ago
It depends on what you're doing. Certainly for standard design you won't be looking at Karnaugh maps. You trust the implementation tool to deal with the logic minimisation for you. In certain cases say a piece of logic on the critical path that's preventing your design clock as fast as you want or something complex that you know requires lots of effort to meet your ppa (power, performance, area) targets, say an ALU or part of an FP unit, you'll be doing more manual optimisation. However even then you're probably not using a Karnaugh map, instead using more sophisticated techniques and then using specialised programs to do these for you (Espresso being the classic example https://en.m.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer https://en.m.wikipedia.org/wiki/Espresso_heuristic_logic_min...). There's also things that simple logic minimisation doesn't take into account like fan out (how many things you have hanging off a particular output) and wire distance (a significant proportion of the clock cycle can be taken up in waiting for signals to propagate if the logic is spread across the chip). A hand crafted piece of logic is likely to use a mix of 'pure logic' type optimization techniques (that are simply trying to minimise logical operations) and the engineer using their judgment to work out what arrangement of minimised functions leads to the best implementation result.
mud_dauber 9y ago
Not that it's day-to-day, but my previous co is still working on a GPU-like design that uses associative memory (with KMs as basic principle) as the core processing engine. It took me forever to wrap my head around the idea. http://www.gsitechnology.com/node/123377 http://www.gsitechnology.com/node/123377

gchadwick 9y ago

It depends on what you're doing. Certainly for standard design you won't be looking at Karnaugh maps. You trust the implementation tool to deal with the logic minimisation for you. In certain cases say a piece of logic on the critical path that's preventing your design clock as fast as you want or something complex that you know requires lots of effort to meet your ppa (power, performance, area) targets, say an ALU or part of an FP unit, you'll be doing more manual optimisation. However even then you're probably not using a Karnaugh map, instead using more sophisticated techniques and then using specialised programs to do these for you (Espresso being the classic example https://en.m.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer https://en.m.wikipedia.org/wiki/Espresso_heuristic_logic_min...). There's also things that simple logic minimisation doesn't take into account like fan out (how many things you have hanging off a particular output) and wire distance (a significant proportion of the clock cycle can be taken up in waiting for signals to propagate if the logic is spread across the chip). A hand crafted piece of logic is likely to use a mix of 'pure logic' type optimization techniques (that are simply trying to minimise logical operations) and the engineer using their judgment to work out what arrangement of minimised functions leads to the best implementation result.

mud_dauber 9y ago

Not that it's day-to-day, but my previous co is still working on a GPU-like design that uses associative memory (with KMs as basic principle) as the core processing engine. It took me forever to wrap my head around the idea. http://www.gsitechnology.com/node/123377 http://www.gsitechnology.com/node/123377