3 ms·

Couldn't you use something like GCC function multi-versioning?

by tambre 9y ago

dragontamer 9y ago
AVX512 has so many more features above-and-beyond Intel's typical SIMD implementation. Feature wise, its beginning to be competitive against NVidia's PTX CUDA architecture. Like, AVX512 is a really, really good instruction set (or I guess: a really good set of instruction sets). Assuming AVX512 F, CD, VL, DQ, and BW (the expected AVX512 instructions in CannonLake): * AVX512F -- "Standard" 512-bit arithmetic already has major improvements, above and beyond the 256bit -> 512bit upgrade. AVX512 has 32-registers per core (when AVX2 and earlier only have 16). The new set of opmask instructions also allow for way more code to turn into "branch-free" code which is friendly for pipelines. This is already a major step forward alone with huge implications for multimedia code. * AVX512-CD: Conflict Detection. These instructions allow auto-vectorizers to "resolve loop conflicts" and auto-vectorize more code. * VL, DQ -- Extend AVX512 to Bytes, Shorts, Longs, Long Longs. * BW -- Extend AVX512 to operate on only 256-bit and 128-bits at a time. -------------------- I'm certain that some code, which could not be vectorized in AVX2 (or lower), will be vectorized with AVX512. Maybe even automatically as compiler writers implement high-level features / auto-vectorizers.
- dman 9y ago
  Intel did a self goal here by limiting availability of AVX512 to select Xeon SKUs.
- jabl 9y ago
  I wonder why they did the BW thing instead of just defining a vector length register like other vector ISA's (which would have allowed to get rid of a remainder loop, leading to less code bloat and more efficient execution for short loops where the number of iterations is not an integer multiple of the ISA vector length).
- thecompilr 9y ago
  VL - Extend AVX512 to operate on only 256-bit and 128-bits at a time. (vector length extension) DQ - Extend AVX512 to Longs, Long Longs. (double word and quadword extension) BW - Extend AVX512 to Bytes, Shorts. (byte and word extension)
jsheard 9y ago
Yep. If you use Intel ISPC to write vector code (and you should, it's seriously underrated) it can also target multiple instruction sets and dispatch to the best supported one at runtime.
Fronzie 9y ago
Yes, that or manual runtime dispatching. Which is doable if there are only a few hot-spots in the code. It'd be so sweet if multi-versioning became well supported across all major compilers (including MSVC)

Couldn't you use something like GCC function multi-versioning?

by tambre 9y ago

Couldn't you use something like GCC function multi-versioning?

AVX512 has so many more features above-and-beyond Intel's typical SIMD implementation. Feature wise, its beginning to be competitive against NVidia's PTX CUDA architecture. Like, AVX512 is a really, really good instruction set (or I guess: a really good set of instruction sets). Assuming AVX512 F, CD, VL, DQ, and BW (the expected AVX512 instructions in CannonLake): * AVX512F -- "Standard" 512-bit arithmetic already has major improvements, above and beyond the 256bit -> 512bit upgrade. AVX512 has 32-registers per core (when AVX2 and earlier only have 16). The new set of opmask instructions also allow for way more code to turn into "branch-free" code which is friendly for pipelines. This is already a major step forward alone with huge implications for multimedia code. * AVX512-CD: Conflict Detection. These instructions allow auto-vectorizers to "resolve loop conflicts" and auto-vectorize more code. * VL, DQ -- Extend AVX512 to Bytes, Shorts, Longs, Long Longs. * BW -- Extend AVX512 to operate on only 256-bit and 128-bits at a time. -------------------- I'm certain that some code, which could not be vectorized in AVX2 (or lower), will be vectorized with AVX512. Maybe even automatically as compiler writers implement high-level features / auto-vectorizers.

dman 9y ago
Intel did a self goal here by limiting availability of AVX512 to select Xeon SKUs.
jabl 9y ago
I wonder why they did the BW thing instead of just defining a vector length register like other vector ISA's (which would have allowed to get rid of a remainder loop, leading to less code bloat and more efficient execution for short loops where the number of iterations is not an integer multiple of the ISA vector length).
thecompilr 9y ago
VL - Extend AVX512 to operate on only 256-bit and 128-bits at a time. (vector length extension) DQ - Extend AVX512 to Longs, Long Longs. (double word and quadword extension) BW - Extend AVX512 to Bytes, Shorts. (byte and word extension)

jsheard 9y ago

Yep. If you use Intel ISPC to write vector code (and you should, it's seriously underrated) it can also target multiple instruction sets and dispatch to the best supported one at runtime.

Fronzie 9y ago

Yes, that or manual runtime dispatching. Which is doable if there are only a few hot-spots in the code. It'd be so sweet if multi-versioning became well supported across all major compilers (including MSVC)