The way I implemented it was with a "memory" class that provides the memory map intrinsic to the system itself. When I load the ROM, I identify the mapper speci

The way I implemented it was with a "memory" class that provides the memory map intrinsic to the system itself. When I load the ROM, I identify the mapper specified in the iNES header. There's a mapper class that basically provides the NROM variants, and classes derived from that (one per mapper family) to implement the ASICs. I have toy-emulator-colored glasses ;-) I've got a few mappers written, but never tried to tackle MMC3 or MMC5, just because the CPU code isn't well-situated to handle most interrupts properly right now. It's been a while since I've thought about that part of the code, but I think that the mappers might be aware of the current PPU cycle (or could be easily wired to be) to support some kind of frame-dependent addressing.