Here are the logic levels in standard VHDL: https://www.cs.sfu.ca/~ggbaker/reference/std_logic/1164/std_logic.html https://www.cs.sfu.ca/~ggbaker/reference/std

Here are the logic levels in standard VHDL: https://www.cs.sfu.ca/~ggbaker/reference/std_logic/1164/std_logic.html https://www.cs.sfu.ca/~ggbaker/reference/std_logic/1164/std_... Maybe some of those can be multiplexed to create Ternary chips with todays tools?