DRAM access is always going to be variable by nature, though they reduce the problem somewhat by never reordering loads and stores. Stores will always write bac

DRAM access is always going to be variable by nature, though they reduce the problem somewhat by never reordering loads and stores. Stores will always write back to D$1 cache and only hit DRAM when a line needs to be flushed from the last level cache, so assuming your data and code fits in cache you can theoretically have 100% determinism (although all of the specific latency numbers are model-dependent, so just like a traditional DSP you'll have to tune for each target).