3 ms·

There is still variable timing depending on whether the needed data happens to be in cache or not. Not sure how hard it is to code in such a way that it is pred

• snuxoll 9y ago
  DRAM access is always going to be variable by nature, though they reduce the problem somewhat by never reordering loads and stores. Stores will always write back to D$1 cache and only hit DRAM when a line needs to be flushed from the last level cache, so assuming your data and code fits in cache you can theoretically have 100% determinism (although all of the specific latency numbers are model-dependent, so just like a traditional DSP you'll have to tune for each target).
  • SAI_Peregrinus 9y ago
    It's also worth noting that hard real-time systems tend to be custom designed, and often for high-budget products like medical devices or test equipment. So it is probably possible to add a bunch of SRAM to the board, and guaranteed latency to that memory is very easy.