3 ms·

Curious how applicable the Mill is for real time use cases Other end is that with the instruction set not being binary stable, I'm curious how well the Mill wo

by __s 9y ago

Curious how applicable the Mill is for real time use cases Other end is that with the instruction set not being binary stable, I'm curious how well the Mill would be useful for something like Singularity https://en.wikipedia.org/wiki/Singularity_%28operating_system%29 https://en.wikipedia.org/wiki/Singularity_%28operating_syste... or a hypothetical WebAssembly OS where userspace programs are an IR for the OS to compile. IIRC the Mill is suppose to have it's own IR for program portability Binary translation viability is key if they want to support Windows-- see current Windows 10 for ARM

SAI_Peregrinus 9y ago
4:30 in the linked video or so: it's statically scheduled, in-order, and all opcodes have fixed execution latency. Should be good for real time.
- ema 9y ago
  There is still variable timing depending on whether the needed data happens to be in cache or not. Not sure how hard it is to code in such a way that it is predictable what data is gonna be in cache at which times.
  - snuxoll 9y ago
    DRAM access is always going to be variable by nature, though they reduce the problem somewhat by never reordering loads and stores. Stores will always write back to D$1 cache and only hit DRAM when a line needs to be flushed from the last level cache, so assuming your data and code fits in cache you can theoretically have 100% determinism (although all of the specific latency numbers are model-dependent, so just like a traditional DSP you'll have to tune for each target).
    - SAI_Peregrinus 9y ago
      It's also worth noting that hard real-time systems tend to be custom designed, and often for high-budget products like medical devices or test equipment. So it is probably possible to add a bunch of SRAM to the board, and guaranteed latency to that memory is very easy.

3 ms·

Curious how applicable the Mill is for real time use cases Other end is that with the instruction set not being binary stable, I'm curious how well the Mill wo

by __s 9y ago

SAI_Peregrinus 9y ago
4:30 in the linked video or so: it's statically scheduled, in-order, and all opcodes have fixed execution latency. Should be good for real time.
- ema 9y ago
  There is still variable timing depending on whether the needed data happens to be in cache or not. Not sure how hard it is to code in such a way that it is predictable what data is gonna be in cache at which times.
  - snuxoll 9y ago
    DRAM access is always going to be variable by nature, though they reduce the problem somewhat by never reordering loads and stores. Stores will always write back to D$1 cache and only hit DRAM when a line needs to be flushed from the last level cache, so assuming your data and code fits in cache you can theoretically have 100% determinism (although all of the specific latency numbers are model-dependent, so just like a traditional DSP you'll have to tune for each target).
    - SAI_Peregrinus 9y ago
      It's also worth noting that hard real-time systems tend to be custom designed, and often for high-budget products like medical devices or test equipment. So it is probably possible to add a bunch of SRAM to the board, and guaranteed latency to that memory is very easy.