6 ms·

Is there a video that explains the Mill CPU in detail but isn't 15 hours long? I could go for 2 or 3 hours.

loup-vaillant 9y ago
I've seen a number of those, and I'm pretty sure there's no way to condense a detailed explanation down to 3 hours while still being accessible to non-specialists. Even the current videos all begin with a "gross oversimplification" disclaimer, so they're probably not very detailed to begin with.
- wtallis 9y ago
  I think it would be possible to describe everything novel with the Mill in three hours (at least the stuff that's been made public so far). It probably wouldn't be possible to even begin covering the implications: how to use the novel features to achieve better performance or security. They did an entire talk on how to translate a switch block into Mill assembly; that talk didn't really introduce any new hardware features, just describe how to use them.
  - loup-vaillant 9y ago
    Probably. But you'd have to be a specialist to infer the implications. I gather they wanted to be accessible to a wider audience.
ithkuil 9y ago
FWIW I wholeheartedly recommend watching all the material about the mill CPU; I found it deeply refreshing and illuminating. (disclaimer: I'm a software engineer, with basic knowledge about hw)
- monk_e_boy 9y ago
  I've watched a few. But I don't need 15 hours of info, 3 is fine :) I'm not THAT interested (yet!)
mcshaner1 9y ago
There are a couple shorter videos with Hackaday, Mill CPU for Humans.
Scaevolus 9y ago
This forum post is the best summary I've seen: https://millcomputing.com/topic/introduction-to-the-mill-cpu-programming-model-2/ https://millcomputing.com/topic/introduction-to-the-mill-cpu... It links to videos with longer explanations.
Symmetry 9y ago
The wiki is probably the best resource then? http://millcomputing.com/wiki/Architecture http://millcomputing.com/wiki/Architecture EDIT: But to summarize: This is an exposed pipeline VLIW design except that the instructions are variable width so it doesn't really fit in the traditional conception of VLIW. There are a bunch of clever tricks for compressing the instruction stream and minimizing fetch bandwidth. Instead of registers recent results go into a static single assignment mechanism called the belt where the last N results are visible. To better handle memory speculation register contents are essentially wrapped in Maybe monads in a way that cleverly gets around the Itanium's problems with memory speculation. To better handle data pressure new pages can be declared in the cache hierarchy full of zeroes and are only assigned backing DRAM when ejected. The caches all work in terms of virtual addresses, translation to physical only happens at the DRAM interface. The stack is managed in hardware with its own dedicated queue, the Spiller, which will start pushing data to L2 on its own as it starts to fill up. Code for the Mill is first written to something called general assembly which assumes every possible instruction, infinite execution width, etc. A single pass specialization step goes through and performs necessary substitutions when an executable at the dynamic linking stage.

I've seen a number of those, and I'm pretty sure there's no way to condense a detailed explanation down to 3 hours while still being accessible to non-specialists. Even the current videos all begin with a "gross oversimplification" disclaimer, so they're probably not very detailed to begin with.

wtallis 9y ago
I think it would be possible to describe everything novel with the Mill in three hours (at least the stuff that's been made public so far). It probably wouldn't be possible to even begin covering the implications: how to use the novel features to achieve better performance or security. They did an entire talk on how to translate a switch block into Mill assembly; that talk didn't really introduce any new hardware features, just describe how to use them.
- loup-vaillant 9y ago
  Probably. But you'd have to be a specialist to infer the implications. I gather they wanted to be accessible to a wider audience.

ithkuil 9y ago

FWIW I wholeheartedly recommend watching all the material about the mill CPU; I found it deeply refreshing and illuminating. (disclaimer: I'm a software engineer, with basic knowledge about hw)

monk_e_boy 9y ago
I've watched a few. But I don't need 15 hours of info, 3 is fine :) I'm not THAT interested (yet!)

mcshaner1 9y ago

There are a couple shorter videos with Hackaday, Mill CPU for Humans.

Scaevolus 9y ago

This forum post is the best summary I've seen: https://millcomputing.com/topic/introduction-to-the-mill-cpu-programming-model-2/ https://millcomputing.com/topic/introduction-to-the-mill-cpu... It links to videos with longer explanations.

Symmetry 9y ago

The wiki is probably the best resource then? http://millcomputing.com/wiki/Architecture http://millcomputing.com/wiki/Architecture EDIT: But to summarize: This is an exposed pipeline VLIW design except that the instructions are variable width so it doesn't really fit in the traditional conception of VLIW. There are a bunch of clever tricks for compressing the instruction stream and minimizing fetch bandwidth. Instead of registers recent results go into a static single assignment mechanism called the belt where the last N results are visible. To better handle memory speculation register contents are essentially wrapped in Maybe monads in a way that cleverly gets around the Itanium's problems with memory speculation. To better handle data pressure new pages can be declared in the cache hierarchy full of zeroes and are only assigned backing DRAM when ejected. The caches all work in terms of virtual addresses, translation to physical only happens at the DRAM interface. The stack is managed in hardware with its own dedicated queue, the Spiller, which will start pushing data to L2 on its own as it starts to fill up. Code for the Mill is first written to something called general assembly which assumes every possible instruction, infinite execution width, etc. A single pass specialization step goes through and performs necessary substitutions when an executable at the dynamic linking stage.