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> because it turns out that getting high performance from an ISA with only simple and relatively large instructions is actually rather difficult That is not th
by nickik 9y ago
> because it turns out that getting high performance from an ISA with only simple and relatively large instructions is actually rather difficult
That is not the reason. Its actually far easier to build a fast MISP or RISC-V Out-of-order CPU then it is a x86. Even if you do it for both the MIPS/RISC-V will run with lower energy and less area.
If you look at a ISA countsy you will see that MISP on 64 Bit is not that far behind x86 and RISC-V is actually ahead in instruction count specially when including the C extension that is in the standard for the Linux ABI.
See: https://www.youtube.com/watch?v=Ii_pEXKKYUg https://www.youtube.com/watch?v=Ii_pEXKKYUg
- userbinator 9y agoEven if you do it for both the MIPS/RISC-V will run with lower energy and less area. http://www.extremetech.com/wp-content/uploads/2014/08/AverageEnergy.png http://www.extremetech.com/wp-content/uploads/2014/08/Averag... That's a 4-way OoO MIPS with 64K L1D and 64K L1C, being far less energy-efficient than 2- and 3-way OoO and in-order(!) x86s and ARMs with half or less L1D and L1C. All results were scaled to 1GHz and 45nm, which already makes x86 look worse and the ARMs and MIPS better than they are in practice. Full article: https://www.extremetech.com/extreme/188396-the-final-isa-showdown-is-arm-x86-or-mips-intrinsically-more-power-efficient https://www.extremetech.com/extreme/188396-the-final-isa-sho...
- snvzz 9y agoMaybe try a Pentium 4. That's x86 too (!).