2 ms·

Oh, I just realized that Roger Espasa, the presenter of this talk, was one of the authors of the Alpha Tarantula paper. Lovely paper back in the day, that showe

by jabl 9y ago

Oh, I just realized that Roger Espasa, the presenter of this talk, was one of the authors of the Alpha Tarantula paper. Lovely paper back in the day, that showed the advantages of a vector ISA compared to spending the transistors on ever-wider superscalar and deeper OoO.

nickik 9y ago
And he works for Esperanto that was found by Dave Ditzel one of the authers (together with David Patterson) of 'The Case for the Reduced Instruction Set Computer' in 1980. These guys know what they are up to, this Vector extension will be awesome.
- jabl 9y ago
  Yes. And further, Ditzel was a co-founder of Transmeta.
  - nickik 9y ago
    Really hope they go after server CPU after the get their feet wet with their ML super computer on a chip they are trying to sell now. Shouldn't be that hard because there already is a general CPU core in their product. It would need some extensions, but nothing they can't handle (Vector unit, crypto). They could get a general RV65GCV out there, that would be awesome.
    - jabl 9y ago
      I hope so too, but I'm not holding my breath. Competing with high-end x86 or POWER for maximum single-thread performance is (with my layman understanding) incredibly expensive. Or if you by server CPU's mean something like the recently announced Qualcomm Centriq, competing mostly in terms of throughput/W/$ while still having decent single-thread performance, that's maybe a step easier but still very expensive. Now, if RISC-V really takes off, I guess at some point we'll see such chips. But "maximum single-thread performance" is probably the last bastion to be attacked.
      - nickik 9y ago
        Totally agree. You don't need "maximum singe-thread performance" to be useful on many server loads. If the energy is cheaper container infrastructure might want to move over. Lets hope that RISC-V can overtake ARM on this. Seems to me that Esperanto could build something along the lines of a Centriq as well if they wanted to get into this. I guess they see more money in ML right now, but its good that ARM is pushing into that market and showing viability of lower power chips.

by jabl 9y ago

nickik 9y ago

And he works for Esperanto that was found by Dave Ditzel one of the authers (together with David Patterson) of 'The Case for the Reduced Instruction Set Computer' in 1980. These guys know what they are up to, this Vector extension will be awesome.

jabl 9y ago
Yes. And further, Ditzel was a co-founder of Transmeta.
- nickik 9y ago
  Really hope they go after server CPU after the get their feet wet with their ML super computer on a chip they are trying to sell now. Shouldn't be that hard because there already is a general CPU core in their product. It would need some extensions, but nothing they can't handle (Vector unit, crypto). They could get a general RV65GCV out there, that would be awesome.
  - jabl 9y ago
    I hope so too, but I'm not holding my breath. Competing with high-end x86 or POWER for maximum single-thread performance is (with my layman understanding) incredibly expensive. Or if you by server CPU's mean something like the recently announced Qualcomm Centriq, competing mostly in terms of throughput/W/$ while still having decent single-thread performance, that's maybe a step easier but still very expensive. Now, if RISC-V really takes off, I guess at some point we'll see such chips. But "maximum single-thread performance" is probably the last bastion to be attacked.
    - nickik 9y ago
      Totally agree. You don't need "maximum singe-thread performance" to be useful on many server loads. If the energy is cheaper container infrastructure might want to move over. Lets hope that RISC-V can overtake ARM on this. Seems to me that Esperanto could build something along the lines of a Centriq as well if they wanted to get into this. I guess they see more money in ML right now, but its good that ARM is pushing into that market and showing viability of lower power chips.