5 ms·

> it has a very simple 8-bit (risc) architecture The 8080/Z80 variant that is used in the Game Boy is not a RISC architecture - it is a processor architecture

> it has a very simple 8-bit (risc) architecture The 8080/Z80 variant that is used in the Game Boy is not a RISC architecture - it is a processor architecture from a time long before the term "RISC" was even used the first time. While the terms RISC/CISC are defined somewhat vaguely, there are still some common properties of architectures that are considered RISC: - Load-store architecture: Counterexample: ADD A,(HL) - Lots of general purpose registers: The 8080 has rather few: B,C,D,E,H,L,A as 8 bit registers and BC,DE,HL,SP as 16 bit registers - Very orthogonal instruction set: Counterexample: AND has always destination A - Often pipelined architecture (though this is not very specific to RISC) - Instructions typically aim to be run in one cycle (when pipelined) Counterexample: Look at the instruction timing tables - very uniform instruction format Look at the instruction encoding

userbinator 9y ago
- very uniform instruction format Look at the instruction encoding The instruction encoding is quite regular -- it follows the 2-3-3 pattern that came from the 8008 (if not earlier), and thus looks much better in octal than hex: http://www.pastraiser.com/cpu/gameboy/gameboy_opcodes.html http://www.pastraiser.com/cpu/gameboy/gameboy_opcodes.html http://www.z80.info/decoding.htm http://www.z80.info/decoding.htm As for everything else, I would agree with you --- it's not RISC.
- 0xcde4c3db 9y ago
  > the 2-3-3 pattern that came from the 8008 (if not earlier) If memory serves, that pattern has its roots in the PDP-11 instruction encoding.
- wolfgke 9y ago
  > The instruction encoding is quite regular -- it follows the 2-3-3 pattern that came from the 8008 (if not earlier) While it is true (and I am aware of it) that the Z80 instructions follow the 2-3-3 pattern, it is nevertheless not that regular. Best look at the "purest example" for this that is referred in the literature all the time and acted as a model for the criterion that in RISC the instruction format is very regular: the instruction format(s) used by MIPS. Here there only exist 3 different types of instruction (R-type, I-type and J-type) and all have a very regular pattern. One can find very suggestive pictures at > http://homepage.divms.uiowa.edu/~ghosh/1-24-06.pdf http://homepage.divms.uiowa.edu/~ghosh/1-24-06.pdf

userbinator 9y ago

- very uniform instruction format Look at the instruction encoding The instruction encoding is quite regular -- it follows the 2-3-3 pattern that came from the 8008 (if not earlier), and thus looks much better in octal than hex: http://www.pastraiser.com/cpu/gameboy/gameboy_opcodes.html http://www.pastraiser.com/cpu/gameboy/gameboy_opcodes.html http://www.z80.info/decoding.htm http://www.z80.info/decoding.htm As for everything else, I would agree with you --- it's not RISC.

0xcde4c3db 9y ago
> the 2-3-3 pattern that came from the 8008 (if not earlier) If memory serves, that pattern has its roots in the PDP-11 instruction encoding.
wolfgke 9y ago
> The instruction encoding is quite regular -- it follows the 2-3-3 pattern that came from the 8008 (if not earlier) While it is true (and I am aware of it) that the Z80 instructions follow the 2-3-3 pattern, it is nevertheless not that regular. Best look at the "purest example" for this that is referred in the literature all the time and acted as a model for the criterion that in RISC the instruction format is very regular: the instruction format(s) used by MIPS. Here there only exist 3 different types of instruction (R-type, I-type and J-type) and all have a very regular pattern. One can find very suggestive pictures at > http://homepage.divms.uiowa.edu/~ghosh/1-24-06.pdf http://homepage.divms.uiowa.edu/~ghosh/1-24-06.pdf