That's exactly what I said when someone wanted to know how to get RISC-V way up there in clock rate or single-threaded. The other possibility was semi-custom jo

That's exactly what I said when someone wanted to know how to get RISC-V way up there in clock rate or single-threaded. The other possibility was semi-custom job at AMD or something. Just implement it in microcode with a little extra hardware if necessary. Reuse tens to hundreds of millions of silicon development. If not high in single-threaded but open, I suggested using Leon3 GPL for fast development or OpenSPARC for lots of cores. OpenPITON already taped out a 25-core chip on 32nm SOI based on OpenSPARC. Many academics used Leon for designs whether taping out or not. IBM is different, though, in that they have a legacy system effect. Their locked-in customers are where this money is coming from. That's why they keep making the stuff to sell for exhorbitant rates. They really need to create different tiers of pricing justifying it by saying the firmware or whole stack is optimized for this, that, etc. If it's gravy train business, that optimized stack is priced at the fortune the marketing team says it's worth. If it's not (i.e. Raptor or RISC-V), it gets a steep discount just to encourage more adoption with associated software porting. They seem too dumb to do this.