Whilst most CPUs do imply a data dependency barrier on the read when a memory access depends on a read, not all do, so it may not be relied on. That and the Al

Whilst most CPUs do imply a data dependency barrier on the read when a memory access depends on a read, not all do, so it may not be relied on. That and the Alpha having a split cache where one half can be more up-to-date than the other, really sound like a lot of fun.