The thing is that it doesn’t matter how many cores you have if they cannot communicate with each other, memory, and IO with performance and relative ease of pro

The thing is that it doesn’t matter how many cores you have if they cannot communicate with each other, memory, and IO with performance and relative ease of programmability. Supporting this many cores requires a network-on-chip which adds latency and complexity to all operations where a core must access resources outside of itself. There is no way that these things could achieve reasonable throughput without a particularly convinient workload and very low level programming. Systolic matrix multiplication on a array of cores connected in a toroidal network-on-chip for example (see Adaptive’s chips). There is no way that this thing has cache coherency. If your lucky it might have some hardware mailbox/mutex/semaphore to help keep all the cores in sync. Really if you want this many ALUs gang them together into a vector machine like a GPU! Anyway, all just speculation; there’s no substantiative details on the announcement or their site. Not that I don’t want to see new and interesting things in computer hardware; I do! I just think that iterating away on the RISC is not the way to make leaps and bounds.