4 ms·
The P4 NetBurst architecture used very deep pipelines, which allowed it to be clocked very fast. To fill that pipeline the scheduler had to predict a lot of bra
by angry_octet 9y ago
The P4 NetBurst architecture used very deep pipelines, which allowed it to be clocked very fast. To fill that pipeline the scheduler had to predict a lot of branches. So if your code had an unrolled loop then it performed well. However, if the scheduler mispredicted branches then the time to flush all those wrong branches and refill the pipeline caused severe inefficiencies. The 'speed demon' design also suffered from power dissipation problems, excess leakage current at high frequencies.
The Core architecture did away with the super deep pipelines, and it sounds like that avoided a particularly pathological case in your application.
- acqq 9y agoIn 2004 there was already 2 MB cache Pentium M whereas Pentiums 4 had only 512 MB (4 times less). Core came out in 2006.