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This is one of the raging debates within the RISC-V group and elsewhere. Is weak memory semantics really worth it or can x86 style TSO be implemented optimally.
by gsmadhusudan 9y ago
This is one of the raging debates within the RISC-V group and elsewhere. Is weak memory semantics really worth it or can x86 style TSO be implemented optimally.Lot of anecdotal evidence but no conclusive experiment. As part of our work we hope to try multiple memory models in our I-class and get some definitive answers.RISC-V by the way supports ARM/PPC style weak memory model or optionally an x86 style TSO.
- bonzini 9y agoARM/PPC is fine, but Alpha took it too far in my opinion (and also didn't have a read memory barrier instruction---nowadays acquire and release memory barriers would probably be preferrable).