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As the lead architect of Shakti and the guy who helped kick-start the project, I figure I am owed my 2 cents ! 1. We never positioned it as an ARM killer ! Tha
by gsmadhusudan 9y ago
As the lead architect of Shakti and the guy who helped kick-start the project, I figure I am owed my 2 cents !
1. We never positioned it as an ARM killer ! That was the imagination of the reporter who wrote the article.
2. Shakti is not a state only project. Parts of Shakti are funded by the govt, these relate to cores and SoCs needed by the Govt. The defense and strategic sector procurement is huge, runs in the 10s of billions of USD.There is significant funding in terms of manpower, tools and free foundry shuttles provided by the private sector. In fact Shakti has more traction with the private sector than the govt sector in terms of immediate deployments.
3. The CPU eco-system including ARM's is a bit sclerotic. It is not the lic cost that is the problem, it is the inherent lack of flexibility in the model.
4. Shakti is not only a CPU. Other components include a new interconnect based on SRIO, GenZ with our extensions accompanied by open source silicon, a new NVMe+ based storage standard again based on open source SSD controller silicon (using Shakti cores of course), open source Rust based MK OS for supporting tagged ISAs for secure Shakti variants, fault tolerant variants for aerospace and ADAS applications, ML/AI accelerators based on our AI research (we are one of the top RL ML labs around).
4. the Shakti program will also deliver a whole host of IPs including the smaller trivial ones and also as needed bigger blocks like SRIO, PCIe and DDR4. All open source of course.
5. We are also doing our own 10G and 25G PHYs
6. A few startups will come out of this but that can wait till we have a good open source base.
7. The standard cores coming out of IIT will be production grade and not research chips.
And building a processor is still tough these days. Try building a 16 core, quad wide server monster with 4 DDR4 channels, 4x25G I/O ports, 2 ports for multi-socket support. All connected via a power optimized mesh fabric. Of course you have to develop the on-chip and off-chip cache coherency stuff too !
8. And yes we are in talks with AMD for using the EPYC socket. But don't think they will bite.
Just ignore the India bit and look at what Shakti aims to achieve, then you will get a better picture.
I have no idea how successful we will be and I frankly do not care. What we will achieve (and have to some extent already) is
- create a critical mass of CPU architects in India
- create a concept to fab eco-system ind India for designing any class of CPUs
- add a good dose of practical CPU design knowhow into the engineering curriculum
- become one of the top 5 CPU arch labs around
Shakti is already going into production. The first design is actually in the control system of an experimental civilian nuclear reactor. IIT is within the fallout zone so you can be sure we will get the design right. If you want any further info, mail me. My email is on the Shakti site.
G S Madhusudan
- gsmadhusudan 9y agoAlso everyone is welcome to review our code and to contribute to the codebase. It is an open source project. IIT-M incubated it but we want it to be community driven. FPGA based dev packages should be announced by jan , based on standard low cost FPGA boards. Dev parts based on ASIC parts will probably be announced 2nd quarter of next year assuming Feb/March tapeout.We would be glad to help other universities do their own tapeouts. One of the goals of Shakti is also to demystify the backend process.
- ikamthania 9y agoCongratulation on the project. Where can one find the source? Is this the one? https://bitbucket.org/casl/shakti_public https://bitbucket.org/casl/shakti_public
- gsmadhusudan 9y agoYes, we will update the C Class next month since our private line has a lot of foundry specific code that needs to be removed. The I class needs more work but the design is in place. It will also move to quad issue and would be a Cortex A72/75 class core. More importantly the basic slow IPs, UART, I2C, quad/Octal SPI, SDRAM controller, JTAG, DMA, PLIC will be FPGA and silicon proven and production quality. Will be very useful to other developers (non RISC-V also) as would the AXI bus.
- urmish 9y agoThis looks very interesting. Its high time an Indian institution has some framework for designing semiconductor chips from scratch and perhaps even mass manufacture them for selling them to the rest of the world. My question is about Bluespec SV and the random logic synthesis of the written code. Is it good enough for good power consumption figures or is that not really a concern at this point? Do you know how its reception has been in industries in the last 4-5 years? Is it still the 'technology of the future'? Another question I have is, this project being open source, are you seeing contributions from other educational institutions or industries? What would be needed get more institutions involved?
- 9y ago