Generally a cache miss to DRAM is going to be somewhere around 3 orders of magnitude slower than accessing something in L1. All it takes is 4-5 of these and no

Generally a cache miss to DRAM is going to be somewhere around 3 orders of magnitude slower than accessing something in L1. All it takes is 4-5 of these and now you're incurring performance hit of ~1ms which gets you into SSD territory[1]. As always, profile before making these optimizations but the OP was asking why something like this isn't possible in managed languages. [1] https://arstechnica.com/information-technology/2012/06/inside-the-ssd-revolution-how-solid-state-disks-really-work/ https://arstechnica.com/information-technology/2012/06/insid...