There is only so far you can shrink. Also Intel’s architecture is way more complex, due to legacy support. Qualcomm for example do not support ARM 32 bit instru

There is only so far you can shrink. Also Intel’s architecture is way more complex, due to legacy support. Qualcomm for example do not support ARM 32 bit instructions at all, only the new 64-bit ones. If Intel could do the same, they would be better off. Alas it’s too late. I think if they went this way with Itanium, 64-bit, fixed sized ISA, instead of VLIW it would be wise. Just thinking about the complexity of the decoder that jas to cope with intructions ranging from 1 byte to 32 byte!