4 ms·
Ultrafast magnetic reversal points the way toward speedy, low-power memory
- korethr 9y agoMy first thought upon reading this was that it sounded kinda like magnetic-core memory. Assuming this tech can be produced at commercial scales and does not remain just a lab experiment, how many years is it going be before "core", is once again slang for the computer's random access memory, instead of the number of compute units in the CPU? Or will perhaps some new slang come to be?
- chiph 9y agoReminds me of Bubble Memory from the late 1980's. It used a magnetic field to push magnetic domains ("bubbles") along a track and eventually they'd get to a read/write zone. So, sequential access but things could be parallelized by having multiple read/write zones. Flash memory came along and was better, so bubble memory was abandoned. https://en.wikipedia.org/wiki/Bubble_memory https://en.wikipedia.org/wiki/Bubble_memory
- blacksmith_tb 9y agoInteresting that Gadolinium was used in bubble memory as well: "Gadolinium gallium garnet ... was used for imitation diamonds and for computer bubble memory."[1] 1: https://en.wikipedia.org/wiki/Gadolinium#Applications https://en.wikipedia.org/wiki/Gadolinium#Applications
- hacker_9 9y ago“We found that in a magnetic alloy made up of gadolinium and iron, these fast electrical pulses can switch the direction of the magnetism in less than 10 picoseconds. That is orders of magnitude faster than any other MRAM technology.” Would love to see a video of how they even measure something like this, some sort of high frequency electron microscope?
- baybal2 9y agoFor people less deep into semiconductor industry - the unreliable reads is a bigger issue for MRAM now than writes. STT-MRAM already beats hands down everything except for 6T or 8T SRAM. Inherently probabilistic reads is an unique trait of MRAM. If you read the same bit few million times, few reads out of these few millions will be wrong invariably of the data stored in the bit. An easy solution for the problem is to have a controller of some sort that emulates random access on one side, but does some error coding on another. That will be just fine for L2 cache. But you will still have to use SRAM for L1 Microcontrollers can simply do double reads, which is not a problem with their work frequencies. This issue prevents MRAM from becoming the universal storage: you still have a special kind of MRAM for mass storage, another special kind for cache, and another for bulk storage RAM The last exciting development is the move from 180 degree spin torque transfer to 3D cell where reads can be done axially, by writes are done perpendicularly. This has an added benefit of electrically isolating read and write terminals. Write "heads" can be made more resistant to breakdown, read "heads" can be optimized for better sensitivity this way.