I've been writing some ARM assembly lately to basically solve a very specific non linear least squares problem for SLAM (specifically bundle adjustment). I sta

I've been writing some ARM assembly lately to basically solve a very specific non linear least squares problem for SLAM (specifically bundle adjustment). I started with the library everyone uses (g2o), attempted a vectorised c++ implementation, and ultimately decided it would be easier to develop in assembly. I've been taking measurements as I go. C++ (g2o) ~ 10-16x C++ (NEON intrinsics) ~ 1.5-2x ASM 1x In this case register layout was very important and GCC isn't able to, for example, arrange for two results to wind up in adjacent 64 bit registers and become a 128bit register. This business of combining registers is an ARMv7 wart and not an issue in Aarch64. In other cases, such as some bilinear interpolation code I wrote, GCC was able to basically generate what was more or less optimal.