"When we get to 3 nm, they can build 16x amount of chips from the same 12 inch wafer." That's only if they are not up against pad-limited die size. Long ago pe

"When we get to 3 nm, they can build 16x amount of chips from the same 12 inch wafer." That's only if they are not up against pad-limited die size. Long ago people were running up against the issue of pad-limited die size, where the size of the I/O ring set the die size while the core logic ended up using less than all the available area. People were trying to figure out what extra stuff to throw into the core since it was shrinking so fast and the I/O was not. That was usually more memory, but that wasn't always useful. So what's happening on that front these days? Are the current architectures actually able to make use of many more cores and memory without blowing up the I/O count of the chip?