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Here are my understandings: Today we are @ ~ 14, 16 nm. When we get to 7nm, the today's chip that is using 1 cm^2 size silicon can probably be build w

by srcmap 9y ago

Here are my understandings: Today we are @ ~ 14, 16 nm. When we get to 7nm, the today's chip that is using 1 cm^2 size silicon can probably be build with 0.25 cm^2 size silicon die. (IO pads are another factor). If "everything (mainly yield?) being equal ", they should be able build 4x amount of chips from the same silicon wafer. Again, assuming IO is not an issue. If the process cost, yield is similar, the new chips "can be" 4x cheaper OR they can pack 4 times # of transistors into the same 1 cm^2 area. It can means more CPU, GPU cores, much larger L1, L2, L3 cache for the same chip size. When we get to 3 nm, they can build 16x amount of chips from the same 12 inch wafer. Or pack 16x amount of transistors into the same silicon area. A good example is: * Apple A10: https://en.wikipedia.org/wiki/Apple_A10 16 nm: die area of 125 mm2, 3.3 billion * Apple A11: https://en.wikipedia.org/wiki/Apple_A11 10 nm: 4.3 billion transistors[6] on a die 87.66 mm2 Small die = more chips per wafer. More transistors = More CPU cores, GPU cores, etc. So nm is definitively has REAL impact on cost of a chip and amount of features (transistors) one can pack into a silicon die. It is not a simple marketing term.

exikyut 9y ago
Code-formatted portion: Today we are @ ~ 14, 16 nm. When we get to 7nm, the today's chip that is using 1 cm^2 size silicon can probably be build with 0.25 cm^2 size silicon die. (IO pads are another factor). If "everything (mainly yield?) being equal ", they should be able build 4x amount of chips from the same silicon wafer. Again, assuming IO is not an issue. If the process cost, yield is similar, the new chips "can be" 4x cheaper OR they can pack 4 times # of transistors into the same 1 cm^2 area. It can means more CPU, GPU cores, much larger L1, L2, L3 cache for the same chip size. When we get to 3 nm, they can build 16x amount of chips from the same 12 inch wafer.
- jamiek88 9y ago
  Thank you! Before you did that I had resigned myself to missing that comment, it was unreadable on mobile.
- geomark 9y ago
  "When we get to 3 nm, they can build 16x amount of chips from the same 12 inch wafer." That's only if they are not up against pad-limited die size. Long ago people were running up against the issue of pad-limited die size, where the size of the I/O ring set the die size while the core logic ended up using less than all the available area. People were trying to figure out what extra stuff to throw into the core since it was shrinking so fast and the I/O was not. That was usually more memory, but that wasn't always useful. So what's happening on that front these days? Are the current architectures actually able to make use of many more cores and memory without blowing up the I/O count of the chip?
danmaz74 9y ago
But the OP asked if 3nm to 10nm is an apples to apples comparison, or if they are instead measuring something different for marketing reasons. In other words: will this "3nm" tech pack 11 times as many transistors as the 10nm tech for the same area?
jlebrech 9y ago
you get to a point where the packaging costs as much as the die, then it doesn't matter how small it gets, you're just recouping the R&D for a smaller manufacturing process.

by srcmap 9y ago

exikyut 9y ago

Code-formatted portion: Today we are @ ~ 14, 16 nm. When we get to 7nm, the today's chip that is using 1 cm^2 size silicon can probably be build with 0.25 cm^2 size silicon die. (IO pads are another factor). If "everything (mainly yield?) being equal ", they should be able build 4x amount of chips from the same silicon wafer. Again, assuming IO is not an issue. If the process cost, yield is similar, the new chips "can be" 4x cheaper OR they can pack 4 times # of transistors into the same 1 cm^2 area. It can means more CPU, GPU cores, much larger L1, L2, L3 cache for the same chip size. When we get to 3 nm, they can build 16x amount of chips from the same 12 inch wafer.

jamiek88 9y ago
Thank you! Before you did that I had resigned myself to missing that comment, it was unreadable on mobile.
geomark 9y ago
"When we get to 3 nm, they can build 16x amount of chips from the same 12 inch wafer." That's only if they are not up against pad-limited die size. Long ago people were running up against the issue of pad-limited die size, where the size of the I/O ring set the die size while the core logic ended up using less than all the available area. People were trying to figure out what extra stuff to throw into the core since it was shrinking so fast and the I/O was not. That was usually more memory, but that wasn't always useful. So what's happening on that front these days? Are the current architectures actually able to make use of many more cores and memory without blowing up the I/O count of the chip?

danmaz74 9y ago

But the OP asked if 3nm to 10nm is an apples to apples comparison, or if they are instead measuring something different for marketing reasons. In other words: will this "3nm" tech pack 11 times as many transistors as the 10nm tech for the same area?

jlebrech 9y ago

you get to a point where the packaging costs as much as the die, then it doesn't matter how small it gets, you're just recouping the R&D for a smaller manufacturing process.