The scaling of marginal vs. NRE costs (not to mention core-limited vs. pad-limited chip area) has put us in the somewhat odd situation that it's actually cheape

The scaling of marginal vs. NRE costs (not to mention core-limited vs. pad-limited chip area) has put us in the somewhat odd situation that it's actually cheaper to crank out an SoC capable of running an emulator than it is to implement the thing you want in < 1% of the transistors.