The phase ordering problem in compilers is notoriously hard. You wouldn't worry about the interaction between strength reduction and scheduling, but in other c

The phase ordering problem in compilers is notoriously hard. You wouldn't worry about the interaction between strength reduction and scheduling, but in other cases you do need to take these interactions into account. In my compiler (aka a compiler I worked on), the software pipeliner estimated register pressure, since you don't want to over-pipeline to expose parallelism if you blow the register set and cause the allocator to spill. Often register allocation is sensitive to the schedule (and there have been attempts to combine them into one pass.) For x+x vs x*2 vs x<<1, the trick is to represent them in a uniform way and let the scheduler decide what instruction to emit based.