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The memory controller may be a more efficient place to do it, because the silicon process is better suited to logic. The challenge is agreeing on how to specify
by tlb 9y ago
The memory controller may be a more efficient place to do it, because the silicon process is better suited to logic. The challenge is agreeing on how to specify limits on access patterns. JEDEC would have to define a protocol for the memory chips to inform the controller of how many accesses per row are allowed between refreshes.
- rasz 9y agotarget row refresh (TRR) is already a thing in laptop DDR4 and is being reported as part of SPD, but it appears Intel still doesnt support it (Cisco claimed Intel does support it, but its hard to believe them when Intel itself never claimed it publicly)