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Software mitigation is not the right way to deal with RAM that can be fooled into flipping bits. All DRAM with this vulnerability should be recalled as defectiv
by tlb 9y ago
Software mitigation is not the right way to deal with RAM that can be fooled into flipping bits. All DRAM with this vulnerability should be recalled as defective. We'd certainly demand that Intel fix a vulnerability that let you flip register bits in other processes by doing something you can do from Javascript.
There are reasonable defenses possible inside the DRAM. They currently depend on the fact that repeated reads of the same data are rare, because of caches. DRAM should insert a delay after hitting the same row N times between refreshes, depending on its analog parameters. It won't affect performance in any normal application.
- RachelF 9y agoTrue. Software is easier to fix than hardware, though. Stopping programmatic cache flushes, or adding timing jitter to them is an easier solution.
- dboreham 9y agoIndeed. Back in the day we called this "pattern sensitivity" and didn't ship product that suffered from it, leading to loss of $$. Collectively the memory industry seems to have screwed up big time, but persuaded everyone they didn't.
- userbinator 9y agoThere are reasonable defenses possible inside the DRAM Don't forget the simplest one: make them like they used to, with a much bigger margin of reliability. Rowhammer wasn't a problem before ~2010 or so, if I remember the original paper correctly. DRAM these days is operating too close to the limits, with razor-thin margins. Indeed, any new DRAM I purchase gets run through a 72-hour stress test and returned as defective if so much as one bit is in error during that time. I like to make an analogy with where flash memory is heading today with multi-level cells (multiplicative capacity increase; exponential endurance and retention decrease) and a phrase to keep in mind: Faster and bigger storage means nothing if it barely works. Contrary to what all the marketing seems to imply, some people actually want memory that works perfectly.
- a3_nm 9y agoI don't want to imply that manufacturers don't have any responsibility in this problem, but I think there's a difference between recalling a defective unit or model from one company, and recalling an entire family of products from different companies... especially if the defect is so common that it could be argued to be part of the design.
- rasz 9y agoYou can also work around it in memory controller incorporating row access counters and forcing refresh after X accesses.
- tlb 9y agoThe memory controller may be a more efficient place to do it, because the silicon process is better suited to logic. The challenge is agreeing on how to specify limits on access patterns. JEDEC would have to define a protocol for the memory chips to inform the controller of how many accesses per row are allowed between refreshes.
- rasz 9y agotarget row refresh (TRR) is already a thing in laptop DDR4 and is being reported as part of SPD, but it appears Intel still doesnt support it (Cisco claimed Intel does support it, but its hard to believe them when Intel itself never claimed it publicly)