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The RISC-V ISA is free (i.e. you can design your own core without paying royalties to a company like ARM, which is what SiFive has done here) but this is a norm
by opencl 9y ago
The RISC-V ISA is free (i.e. you can design your own core without paying royalties to a company like ARM, which is what SiFive has done here) but this is a normal paid-for IP core. They do have some SoCs with a "free and open platform specification" but there's no public repo to download their Verilog code from.
If you want an actual open source RISC-V core, see: https://github.com/lowRISC/lowrisc-chip https://github.com/lowRISC/lowrisc-chip
- monocasa 9y agoThe source here isn't their core? https://github.com/sifive/freedom https://github.com/sifive/freedom
- opencl 9y agoThat code seems to be for an FPGA devkit for their SoC but using an entirely different CPU core, the Berkeley Rocket Chip. They're selling coreplex licenses for several hundred thousand dollars (not the one in the linked product page, it isn't for sale yet): https://dev.sifive.com/coreplex-risc-v-ip/buy/rtl/e51_coreplex/configure/ https://dev.sifive.com/coreplex-risc-v-ip/buy/rtl/e51_corepl...
- monocasa 9y agoSiFive is a bunch of Berkeley people. Are you totally sure that their cores aren't rebranded Rocket cores?
- _chris_ 9y ago> using an entirely different CPU core, the Berkeley Rocket Chip Nope, the U54 and E31 are both Rocket, just with different parameters/configurations. SiFive has continued to improve Rocket and contribute their improvements back to the available source code.
- asb 9y agoHi, I'm one of the co-founders of the lowRISC project. You're right that SiFive's licensing arrangements can be somewhat confusing. Although they sell licenses (like https://static.dev.sifive.com/business/sifive-license-and-support-agreement-sample-e51-20170602.pdf https://static.dev.sifive.com/business/sifive-license-and-su...) which look like a typical proprietary IP agreement, the SiFive Coreplex IP is a derivative of the open-source Rocket chip generator. SiFive was founded by a team from Berkeley who produced Rocket, and are almost certainly now the biggest contributor to ongoing Rocket development.
- phkahler 9y ago>> the SiFive Coreplex IP is a derivative of the open-source Rocket chip generator. Any idea why they didn't drop in the BOOM core then? The EE Times article puts it at 30mm^2 with the L2 cache, so even a larger BOOM core wouldn't increase the die size much. Or are they aiming for really low power first? I could see a whole family of these coming over time. I hope this all goes really well.
- _chris_ 9y agoWhile they could easily drop in a BOOM core, there would be some very non-trivial costs for SiFive to verify the IP and tune up the performance and feature set to match their costumers' needs. A lot of work has been put into Rocket once it made the transition from academic to professional and they would have to do that again for BOOM.
- jabl 9y agoAlso, there was quite recently a BOOMv2 paper describing some improvements, and hints of low-hanging fruits for further work. So I wouldn't be surprised if we'd have at least BOOMv3 before anybody commits to taping it out on ASIC.
- monocasa 9y agoThe BOOMv2 authors apparently had taped it out in TSMC 28 nm HPM.