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This was very interesting, thank you! I'm sure I missed something in your first paragraph though, because the process that you described sounds very much like

This was very interesting, thank you! I'm sure I missed something in your first paragraph though, because the process that you described sounds very much like a normal modern JIT compiler. In V8 and SpiderMonkey for example, the engine starts with the first tier, which is a baseline interpreter that collects type information on each function call, and then if a function is invoked enough times, it compiles the function to machine code using the type information collected in the first tier. There are more tiers up the chain, slower to compile and faster to run, where dataflow analysis is done on the hottest functions, which get optimisations such as inline caching, etc. All that is done on the CPU of course, so I'm curious how an FPGA could help in this process?

jecel 9y ago
JIT is a generic term that applies both to dynamic compilation (one pass) and adaptive compilation (multiple passes with profiling). While it is pretty normal these days, many people involved in FPGA research only know about static languages and manual partitioning (like OpenCL) and that is why I always explain what it is. FPGAs don't help JITs at all. I was saying the opposite: if certain problems (slow compilation and slow reconfiguration) could be solved then JITs could offer the opportunity to generate hardware acceleration on demand that would be tuned for a specific execution of an application.