3 ms·
I have worked on this in the case of Smalltalk and the opportunities are there but there are significant problems. The opportunity is in the form of adaptive co
by jecel 9y ago
I have worked on this in the case of Smalltalk and the opportunities are there but there are significant problems. The opportunity is in the form of adaptive compilation where you initially use a simple compiler (or even an interpreter for the very first execution) and then collect profiling information and call a much better compiler to generate code for the "hot spots". A key optimization is inlining which greatly increases the size of a basic block. You could add a third step for the really, really hot spots and compile to hardware.
With commercial FPGAs you have a problem that you can't generate the bits yourself but have to use the vendor tools. These are pretty simplistic and will take minutes or hours to compile non trivial circuits. What I mean by this is that they flatten the netlist at some point so compilation time grows non linearly with circuit size. So if your design has five identical blocks, adding a sixth might make it take twice as long to compile.
A second problem is that it takes a while to load the bits into the FPGA. The old XC6000 could be accessed as RAM and quickly rewritten but all other models serially shift in the configuration bits. Xilinx allows partial reconfiguration where you can load the bits to one part of the FPGA while the rest continues to work but that is pretty hard to use and the competitors don't even offer this option.
- AriaMinaei 9y agoThis was very interesting, thank you! I'm sure I missed something in your first paragraph though, because the process that you described sounds very much like a normal modern JIT compiler. In V8 and SpiderMonkey for example, the engine starts with the first tier, which is a baseline interpreter that collects type information on each function call, and then if a function is invoked enough times, it compiles the function to machine code using the type information collected in the first tier. There are more tiers up the chain, slower to compile and faster to run, where dataflow analysis is done on the hottest functions, which get optimisations such as inline caching, etc. All that is done on the CPU of course, so I'm curious how an FPGA could help in this process?
- jecel 9y agoJIT is a generic term that applies both to dynamic compilation (one pass) and adaptive compilation (multiple passes with profiling). While it is pretty normal these days, many people involved in FPGA research only know about static languages and manual partitioning (like OpenCL) and that is why I always explain what it is. FPGAs don't help JITs at all. I was saying the opposite: if certain problems (slow compilation and slow reconfiguration) could be solved then JITs could offer the opportunity to generate hardware acceleration on demand that would be tuned for a specific execution of an application.