It sounds like it would be little different from a CPU implemented on an FPGA. True, you want to use run-time info to optimize on the fly, but my guess is that

It sounds like it would be little different from a CPU implemented on an FPGA. True, you want to use run-time info to optimize on the fly, but my guess is that modern branch predictors, caches etc, already do as much of this stuff as we know how to do. In the unforseeable future, then who knows, maybe the predictors will become so flexible that even conventional CPUs evolve into something like basically FPGAs.