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Well, if all chip manufacturers made jtag bsdl files for their parts then no one would need this. But since few do, thanks, very cool innovation!
by zw123456 9y ago
Well, if all chip manufacturers made jtag bsdl files for their parts then no one would need this. But since few do, thanks, very cool innovation!
- natashabaker 9y agoVery true, that would make our jobs much easier!
- metaphor 9y ago> Well, if all chip manufacturers made jtag bsdl files for their parts... BSDLs are designed to define boundary-scan chains, not schematic symbols/footprints.
- zw123456 9y agoThere is a macro available for the Eagle PCB design software that converts BSDL to schematic and foot print. BSDL although originally for boundary scan has info about footprint but it is not a big deal since so few manufacturers make it available.
- metaphor 9y ago> BSDL although originally for boundary scan has info about footprint but it is not a big deal since so few manufacturers make it available. Devil always lurks in the details. That generic parameter is so sparsely defined in 1149.1 that I struggle to see any semblance of consistency between major reconfigurable device vendors, let alone vendors which don't actually integrate boundary-scan. There's also a philosophical point: electrical schematics should document electrical intent. A BSDL-driven EDA approach which must consider arbitrary semiconductors would largely be constrained to simple I/O separation with a mechanical representation of physical package layout serving as fallback in the case of poor inference. This doesn't account for symbolic capability between PCADs either, e.g. multi-part symbols, variants, hidden pins, etc. In summary, end result is pretty much a box with little to no functional intent conveyed, resulting in what I consider to be the worst type of schematic interpretation experience.