4 ms·

Looking forward to CPUs getting on-die FPGAs so we can actually chuck some fully deterministic timing tasks onto them. Even if you're running on metal without a

Looking forward to CPUs getting on-die FPGAs so we can actually chuck some fully deterministic timing tasks onto them. Even if you're running on metal without an OS, there are heaps of things that can stop your code from running with predictable timing, and it seems like it's getting worse as CPUs are getting more complex.

planteen 9y ago
We've had FPGA with CPU for 5 years or so on Xilinx Zynq. :)
- jeff_marshall 9y ago
  Xilinx has being doing CPU+FPGA for longer than that. I did some C runtime enhancements for the PPC 440 included in the FX70 for a product made by a former employer (shadow stacks for better CFI, more locked down MMU use, etc).
- kyzyl 9y ago
  Amusingly, Xilinx makes dev tools that are so unbelievably bad that it's almost impossible to do any of the best practices for development that you would hope for in safety critical systems. No source control, code review, reproducible builds, integration testing, centralized code review, etc. Presumably you can sort of brute force it if you have defense level budgets, but it's a seriously bad situation.
  - planteen 9y ago
    Yeah last time I used Vivado a couple years ago, version control on the project was a nightmare. Reproducible builds seem to be a problem with stock FPGA synthesis tools in general.
greenleafjacob 9y ago
Related: reducing system jitter [1] [1] http://epickrram.blogspot.co.uk/2015/09/reducing-system-jitter.html http://epickrram.blogspot.co.uk/2015/09/reducing-system-jitt...
- agumonkey 9y ago
  simple and super valuable article.
mkj 9y ago
The PRU in some TI chips like that in the Beaglebone give you that kind of thing. A couple of deterministic 200mhz arm cores that run separately from the main cpu. They've been used for lots of motor control projects and also bit-banging network protocols.
- mkj 9y ago
  Correction: they're not ARM, but a different RISC architecture.

planteen 9y ago

We've had FPGA with CPU for 5 years or so on Xilinx Zynq. :)

jeff_marshall 9y ago
Xilinx has being doing CPU+FPGA for longer than that. I did some C runtime enhancements for the PPC 440 included in the FX70 for a product made by a former employer (shadow stacks for better CFI, more locked down MMU use, etc).
kyzyl 9y ago
Amusingly, Xilinx makes dev tools that are so unbelievably bad that it's almost impossible to do any of the best practices for development that you would hope for in safety critical systems. No source control, code review, reproducible builds, integration testing, centralized code review, etc. Presumably you can sort of brute force it if you have defense level budgets, but it's a seriously bad situation.
- planteen 9y ago
  Yeah last time I used Vivado a couple years ago, version control on the project was a nightmare. Reproducible builds seem to be a problem with stock FPGA synthesis tools in general.

greenleafjacob 9y ago

Related: reducing system jitter [1] [1] http://epickrram.blogspot.co.uk/2015/09/reducing-system-jitter.html http://epickrram.blogspot.co.uk/2015/09/reducing-system-jitt...

agumonkey 9y ago
simple and super valuable article.

mkj 9y ago

The PRU in some TI chips like that in the Beaglebone give you that kind of thing. A couple of deterministic 200mhz arm cores that run separately from the main cpu. They've been used for lots of motor control projects and also bit-banging network protocols.

mkj 9y ago
Correction: they're not ARM, but a different RISC architecture.