3 ms·
There have been CPUs with multiple datastacks e.g. https://bernd-paysan.de/4stack.html https://bernd-paysan.de/4stack.html is a VLIW ISA with a very dense encod
by crest 9y ago
There have been CPUs with multiple datastacks e.g. https://bernd-paysan.de/4stack.html https://bernd-paysan.de/4stack.html is a VLIW ISA with a very dense encoding and "just less ports" to the register file than a classic DSP.
- phs2501 9y agoThanks, that's very interesting. Seems like it'd also be "interesting" to write a compiler for though, especially since you have to manage stack hygiene for four stacks simultaneously. And I'm not sure, but doesn't allowing each functional unit to directly read the top four entries of the other FUs' stacks reintroduce some of the kind of potential hazards that the Mill belt (with its SSA-style usage) tries to avoid?