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How does this compare to rocketchip and other RISC-V cores? Which is easiest to get started on with an FPGA? From my looking, rocketchip seems like it is seeing

by ece 9y ago

How does this compare to rocketchip and other RISC-V cores? Which is easiest to get started on with an FPGA? From my looking, rocketchip seems like it is seeing the most active development in open source, but I would love to see a comparison of all open RISC-V cores.

_chris_ 9y ago
BOOM is a core that fits into the rocketchip SoC ecosystem. Or said another way, BOOM wears rocketchip's skin. :D [i.e., caches, memory system, uncore, test harnesses...] Default rocketchip uses the Rocket core, which is a single-issue in-order core. If things are going well, a two-wide BOOM is 50% to 100% faster than Rocket [as measured using SPECint and Coremark]. If you want to get started, I'd recommend starting with rocketchip/sifive dev boards (they provide ready-to-go FPGA images). Rocketchip has a company supporting it, it's open-source, and it will boot Linux (if you use the RV64G version). But it's a very complex code base, so if you want to hack the RTL, it will be a steep learning curve. If you just want to play with smaller, easier to grok cores, you can find some ready-to-go FPGA cores like picorv32. That's targeting high-frequency FPGA softcore applications and is a multi-cycle design (trading off IPC for higher frequencies).
- ece 9y ago
  Thanks for the info. I will have to start with the picorv32 (RV32IM) or Rocket Chip itself and see what will fit on my Papilio board. If I wanted to hack on RTL and a toolchain, is the GCC port or LLVM port easier to start with? There seem to be a couple of LLVM ports... I will go with LLVM-RISCV with RocketChip. Also, any plans of an async RISC-V implementation?
  - _chris_ 9y ago
    The gcc port is mature and has been upstreamed. The LLVM port is still a work-in-progress. I know there's been at least one talk presenting some thesis work on an clock-less RISC-V design at an early RISC-V workshop, but I'm not aware of any in-progress implementations.

by ece 9y ago

_chris_ 9y ago

BOOM is a core that fits into the rocketchip SoC ecosystem. Or said another way, BOOM wears rocketchip's skin. :D [i.e., caches, memory system, uncore, test harnesses...] Default rocketchip uses the Rocket core, which is a single-issue in-order core. If things are going well, a two-wide BOOM is 50% to 100% faster than Rocket [as measured using SPECint and Coremark]. If you want to get started, I'd recommend starting with rocketchip/sifive dev boards (they provide ready-to-go FPGA images). Rocketchip has a company supporting it, it's open-source, and it will boot Linux (if you use the RV64G version). But it's a very complex code base, so if you want to hack the RTL, it will be a steep learning curve. If you just want to play with smaller, easier to grok cores, you can find some ready-to-go FPGA cores like picorv32. That's targeting high-frequency FPGA softcore applications and is a multi-cycle design (trading off IPC for higher frequencies).

ece 9y ago
Thanks for the info. I will have to start with the picorv32 (RV32IM) or Rocket Chip itself and see what will fit on my Papilio board. If I wanted to hack on RTL and a toolchain, is the GCC port or LLVM port easier to start with? There seem to be a couple of LLVM ports... I will go with LLVM-RISCV with RocketChip. Also, any plans of an async RISC-V implementation?
- _chris_ 9y ago
  The gcc port is mature and has been upstreamed. The LLVM port is still a work-in-progress. I know there's been at least one talk presenting some thesis work on an clock-less RISC-V design at an early RISC-V workshop, but I'm not aware of any in-progress implementations.